Microprocessors generally include a variety of logic circuits fabricated on a single semiconductor integrated circuit (IC). These logic circuits typically include a processor core, memory, and other components. More and more high-end processors are now including more than one processor core on the same IC. For instance, multi-core processors such as Chip Multi-Processors (CMPs) for example, feature a multi-core structure that implements multiple processor cores within an IC.
Increased silicon efficiencies are now providing new opportunities for adding additional functionality into the processor silicon. As an example, applications are taking advantage of increased multi-threading capabilities realized from an increased number of processing cores in the same processor. Hence, it is becoming important to develop a communication protocol that optimizes performance of a multi-core processor by mitigating system interconnect latency issues and ensuring that aggregated processor cores appear as one caching agent in order to avoid scalability issues and interconnect saturation.